The present invention relates to the manufacturing of semiconductor devices, and more particularly, to manufacturing a vertical-channel MOSFET transistor.
As is known, a vertical-channel MOSFET transistor has its source and drain regions in layers which have the same type of conductivity and which are parallel to one another and to the front surface of the wafer of semiconductor material in which the transistor is formed. These layers are separated by a body region having the second type of conductivity. The gate dielectric and the gate electrode are formed on the lateral walls of a trench hollowed out in the wafer so as to intersect the source and drain regions. The channel of the MOSFET is included in the portion of the body region delimited by the side walls of the trench.
A technique is known for the manufacture of electronic devices with high dynamic performance, i.e. with a high frequency or fast switching speed, which can achieve the very small dimensions and the extremely thin junctions necessary for such performance. Isolation between active areas of the device is achieved by the hollowing-out of narrow trenches which are filled at least partially with dielectric material (trench isolation). This technique also permits the formation of self-aligned structures with the use of two polycrystalline silicon layers and is therefore known as the xe2x80x9cdouble polysilicon self-alignedxe2x80x9d or DPSA technique.
With this technique, it is possible to produce vertical npn bipolar transistors capable of operating at transition frequencies greater than 50 Ghz. Unfortunately, up to now, this technique has not been suitable for the production of other components of equally good quality, except at the cost of process complications which involve unacceptable increased expense. For example, lateral pnp transistors can be produced without modification of the standard process, but with rather limited performance. There is therefore a need, within the scope of this technology, to produce good-quality circuit components for use in combination with the npn bipolar transistors to extend the application of this technology to the design of more complex integrated circuits.
An object of the present invention is to provide a method of manufacturing a semiconductor device comprising a vertical-channel MOSFET transistor which is compatible with the DPSA technique.
This object is achieved, according to the invention, by a method including steps performed on a wafer of semiconductor material having a layer with n conductivity. First, n impurity ions and p impurity ions are implanted in an area of the layer and the wafer is subjected to a high-temperature treatment. The impurities, the implantation doses and energies, and the high-temperature treatment time and temperature are such as to form a first p region, and a second n region which forms a pn junction with the first region. A trench is hollowed out which intersects the first region and the second region. The method further includes forming a dielectric coating on the lateral surface of the trench, depositing electrically-conductive material in the trench in contact with the dielectric, and forming elements for electrical contact with the n conductivity layer, with the second region, and with the electrically-conductive material inside the trench, to produce drain, source and gate electrodes of the MOSFET, respectively.